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AS3930
Datasheet - D e t a i l e d D e s c r i p t i o n
8.1.4
Data Receiving
After a successful wake-up the chip enters the data receiving mode. In this mode, the chip can be retained as a normal OOK receiver. The
received data are displayed on the DAT pin. It is possible to put the chip back in to listening mode either with a direct command (CLEAR_WAKE,
see Table 12 ) or by using the timeout feature. This feature automatically sets the chip back to listening mode after a certain time defined in the
R7<7:5> .
8.2 System and Block Specification
8.2.1
Main Logic and SDI
Table 6. Register Table
R0
7
n.a.
6
5
ON_OFF
4
3
Reserved
2
1
EN_A
0
PWD
R1
ABS_HY
AGC_TLIM
AGC_UD
ATT_ON
n.a.
EN_PAT2
EN_WPAT
EN_RTC
R2
R3
S_ABSH
HY_20m
W_PAT_T<1:0>
HY_POS
FS_SLC<2:0>
Reserved
S_WU1<1:0>
FS_ENV<2:0>
R4
R5
R6
T_OFF<1:0>
R_VAL<1:0>
TS2<7:0>
TS1<7:0>
GR<3:0>
R7
R8
R9
R10
R11
R12
R13
n.a.
T_OUT<2:0>
n.a.
n.a.
Reserved
n.a.
n.a.
F_WAKE
T_HBIT<4:0>
RSSI1<4:0>
T_AUTO<2:0>
Register Table Description and Default Values.
Table 7. Description and Default Values
Register
R0<5>
R0<4>
R0<3>
R0<2>
R0<1>
R0<0>
R1<7>
R1<6>
R1<5>
R1<4>
R1<3>
R1<2>
R1<1>
R1<0>
Name
ON_OFF
MUX_123
Reserved
Reserved
EN_A
PWD
ABS_HY
AGC_TLIM
AGC_UD
ATT_ON
Reserved
EN_PAT2
EN_WPAT
EN_RTC
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0
0
1
1
1
0
0
0
1
0
0
0
1
1
Description
On/Off operation mode. (Duty-cycle defined in the register R4<7:6> )
Reserved (it is not allowed to set this bit to 1)
Reserved
Reserved
Channel enable
Power down
Data slicer absolute reference
AGC acting only on the first carrier burst
AGC operating in both directions (up-down)
Antenna damper enable
Reserved
Double wake-up pattern correlation
Data correlation enable
Crystal oscillator enable
www.ams.com/LF-Receiver/AS3930
Revision 1.5
12 - 32
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